This application is based upon and claims benefit of priority of Japanese Patent Application No. 2000-390855 filed on Dec. 22, 2000, the content of which is incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor sensor chip having a diaphragm for detecting pressure, acceleration or the like, the semiconductor chip being separated from a semiconductor wafer by dicing.
2. Description of Related Art
It is generally known to form a thin diaphragm for detecting a pressure on a semiconductor sensor chip by making a cavity under an anisotropic etching process. There is a problem, however, that sharp corners are formed at bottom portions of the cavity if the cavity is etched out by the anisotropic etching. Since a stress is concentrated at the sharp corners, a mechanical strength of the thin diaphragm is reduced. JP-A-11-97413 proposes a method for rounding the sharp corners of the cavity by additionally performing electrochemical isotropic etching after the cavity is formed by the anisotropic etching process, thereby to reduce the stress imposed on sharp corners and to improve the mechanical strength of the diaphragm.
Conductor lines have to be formed along column and row dicing lines on the semiconductor wafer to apply a voltage for the electrochemical isotropic etching. In the conventional method, however, it is highly possible that a part of a conductor material forming the conductor lines remains on individual chips after the sensor chip is separated by dicing. If the conductor remains on the semiconductor sensor chip, particles of the conductor adhere to diced-out sides of the sensor chip, and thereby a current leakage occurs on the side surfaces thereof. To prevent the leakage, it is proposed to use a protective diode connected between a sensor circuit and the conductor lines. However, the chip size has to be larger if such a diode is additionally used.
The present invention has been made in view of the above-mentioned problem, and an object of the present invention is to provide an improved semiconductor sensor chip having a diaphragm, in which current leakage is prevented without using a protecting diode. Another object of the present invention is to provide a method of manufacturing such an improved semiconductor sensor chip.
A semiconductor wafer having an upper layer and a lower layer, both layers forming a P-N junction plane therebetween, is prepared. A plurality of sensor elements including strain gauges are formed on the upper layer of the wafer. Each sensor element is separated from one another by interstices running in column and row directions on the wafer. An impurity is diffused in the upper layer to form first diffused layer positioned along the interstices, and further the same impurity is diffused along the P-N junction plane to form second diffused layer positioned underneath the first diffused layers. The impurity density in the first and the second diffused layers is made higher than that of the semiconductor wafer.
Then, conductor lines are formed on the upper layer to cover the first diffused layers. Portions of the lower layer are etched to form diaphragms, each positioned underneath each sensor element. The diaphragms are formed by first performing anisotropic etching and then performing isotropic etching by applying an electrical voltage to the lower layer through the conductor lines and the first and second diffused layers. Corners of cavities formed by the anisotropic etching are rounded by the isotropic etching, thereby to enhance mechanical strength of the diaphragms.
Then, the semiconductor wafer is diced with a dicing blade along the conductor lines formed in the interstices to separate individual sensor chips. A width of the dicing blade is made wider than a width of the conductor lines, so that all of the conductor lines are removed by dicing. Preferably, a width of the first diffused layers formed underneath the conductor lines is made narrower than the width of the conductor lines to ensure all of the first diffused layers are removed by dicing when the conductor lines are all removed. Further, a width of the second diffused layers is made wider than that of the first diffused layers, so that the second diffused layers expose to sides of the semiconductor chips after they are diced out.
Since the conductor lines and the first diffused layers are all removed by dicing, electrical leakage due to leftover particles is surely avoided. Further, the electrical voltage for the isotropic etching is effectively applied to the lower layer through the second diffused layers which are made wider than the first diffused layers. The second diffused layers exposed to the side surfaces of the sensor chip effectively separate the upper layer and the lower layer.
Other objects and features of the present invention will become more readily apparent from a better understanding of the preferred embodiment described below with reference to the following drawings.